Sub-half-micron multi-level interconnection structure and process thereof
US5981374A · kind A · utility
30Cited by
16References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Apr 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the field of semiconductor manufacturing, and more specifically to methods of forming sub-half-micron multi-level interconnect structures for integrated circuits. The inventive structure and process are spike free and that has resulted in improved circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.