Active silicon-on-insulator region having a buried insulation layer with tapered edge
US5982006A · kind A · utility
7Cited by
1References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76267
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An active silicon-on-insulator region isolation structure is provided that includes an active bulk substrate region (24), an active silicon-on-insulator region (22), and a transition region positioned between the active bulk substrate region (24) and the active silicon-on-insulator region (22). The active silicon-on-insulator region (22) includes a silicon-on-insulator film (16) positioned above a buried insulator layer (18). The transition region includes a sloping portion of the buried insulator layer (18) and a tapered edge portion of the silicon-on-insulator film (16).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.