Keith A. Joyner
28Patents
15h-index
23Co-inventors
81Inventor score
Filing activity: Apr 30, 1982 → Jan 5, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6737347B1 | Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device | Electricity | 196 | Expired |
| US5863827A | Oxide deglaze before sidewall oxidation of mesa or trench | Electricity | 94 | Expired |
| US6376285B1 | Annealed porous silicon with epitaxial layer for SOI | Electricity | 67 | Expired |
| US5364800A | Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate | Emerging Cross-Sectional Technologies | 64 | Expired |
| US6806151B2 | Methods and apparatus for inducing stress in a semiconductor device | Electricity | 57 | Expired |
| US5909628A | Reducing non-uniformity in a refill layer thickness for a semiconductor device | Emerging Cross-Sectional Technologies | 36 | Expired |
| US5429955A | Method for constructing semiconductor-on-insulator | Electricity | 29 | Expired |
| US5882981A | Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material | Emerging Cross-Sectional Technologies | 28 | Expired |
| US4507851A | Process for forming an electrical interconnection system on a semiconductor | Emerging Cross-Sectional Technologies | 24 | Expired |
| US5548149A | Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate | Emerging Cross-Sectional Technologies | 22 | Expired |
| US6118161A | Self-aligned trenched-channel lateral-current-flow transistor | Electricity | 21 | Expired |
| US6214699A | Method for forming an isolation structure in a substrate | Electricity | 20 | Expired |
| US6004871A | Implant enhancement of titanium silicidation | Electricity | 20 | Expired |
| US6114741A | Trench isolation of a CMOS structure | Electricity | 19 | Expired |
| US6228747A | Organic sidewall spacers used with resist | Electricity | 16 | Expired |
| US6376859B1 | Variable porosity porous silicon isolation | Electricity | 13 | Expired |
| US6057214A | Silicon-on-insulation trench isolation structure and method for forming | Electricity | 12 | Expired |
| US5440132A | Systems and methods for controlling the temperature and uniformity of a wafer during a SIMOX implantation process | Electricity | 10 | Expired |
| US6207511A | Self-aligned trenched-channel lateral-current-flow transistor | Electricity | 7 | Expired |
| US5982006A | Active silicon-on-insulator region having a buried insulation layer with tapered edge | Electricity | 7 | Expired |
| US7101772B2 | Means for forming SOI | Electricity | 4 | Expired |
| US5352341A | Reducing leakage current in silicon-on-insulator substrates | Electricity | 4 | Expired |
| US6180491A | Isolation structure and method | Electricity | 4 | Expired |
| US6767777B2 | Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers | Electricity | 4 | Expired |
| US7339214B2 | Methods and apparatus for inducing stress in a semiconductor device | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.