Faster NAND for microprocessors utilizing unevenly sub-nominal P-channel and N-channel CMOS transistors with reduced overlap capacitance
US5982199A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Jan 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided an improved NAND logic gate circuit for use in microprocessors and a method for fabricating the same so as to be capable of operating at higher speeds. The NAND logic gate circuit includes a parallel structure formed of a plurality of P-channel MOS together in parallel and a stacked structure formed of a plurality of N-channel MOS transistors all connected together in series. Each of the plurality of P-channel MOS transistors has a first sub-nominal channel length and reduced overlap capacitance. Each of the plurality of N-channel MOS transistors has a second sub-nominal channel length and reduced overlap capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.