PNP driven NMOS ESD protection circuit
US5982217A · kind A · utility
24Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Feb 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.