Memory cell capable of storing more than two logic states by using different via resistances
US5982659A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.