EDRAM having a dynamically-sized cache memory and associated method
US5983313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1996 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Apr 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.