Method of repairing semiconductor memory, electron-beam memory repairing apparatus and redundancy memory circuit to which the method of repairing semiconductor memory is applicable
US5985677A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 21, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | May 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.