Semiconductor device manufacturing method
US5985747A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An underlying Al alloy wiring 3 and an inter-layer insulation film 4 are formed sequentially on a semiconductor substrate 1 via an inter-layer insulation film 2. An inter-layer insulation film 5 highly hygroscopic and containing much moisture is made and etched back to flush depressions by the underlying Al alloy wiring 3. After an inter-layer insulation film 6 is made, a contact-hole C is made in the inter-layer insulation films 6 and 4. After that, prior to making a TiN/Ti film 7, gases are removed from the inter-layer insulation films 4 through 6 by annealing. The TiN/Ti film 7 is made as thick as 80 nm. In an alternative version, after the inter-layer insulation film is etched back, annealing is done to remove gases especially from the inter-layer insulation film 5. In another alternative version, a protective film 9 is made on the side wall of the contact-hole C, or the surface of the inter-layer insulation films 6 and 4 having formed the contact-hole or the surface of the inter-layer insulation film 5, is nitrified, to prevent degassing of the inter-layer insulation films 4 through 6.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.