Semiconductor integrated circuit device having multi-level wiring capacitor structures
US5986299A · kind A · utility
25Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.