Protection circuit for output drivers
US5986867A · kind A · utility
18Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A DRAM output protection circuit (100). A dummy NMOS transistor (116) is connected in parallel with the NMOS output transistor (102). The gate of the dummy transistor (116) is connected through a resistor (122) to ground (108). The resistor 122 value and the gate capacitance (121,127) of the dummy transistor (116) are adjusted to achieve the desired gate matching between the dummy transistor gate (120) and the NMOS output transistor gate (110).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.