Synchronous read only memory device
US5986918A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jul 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory device having a given burst length comprises: a memory cell array having a plurality of memory cells, each of the memory cell storing a data bit; a pass gate circuit having a plurality of pass gate blocks assigned to a plurality of bit lines coupled to the memory cells; a sense amplifier circuit having a plurality of sense amplifiers connected to the pass gate blocks with a given ratio thereof; decoding means for causing the pass gate circuit to transfer a given number of the data bits from the memory cells to the sense amplifier circuit; and means for receiving the data bits from the sense amplifier circuit and for outputting a plurality of data bits corresponding to the burst length in a given operation mode. The memory device preferably conducts in a sequential mode or interleave mode, with a pipelined data output configuration according to the burst length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.