Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system
US5987579A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.