Method for analyzing contamination within hole in semiconductor device
US5989919A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N33/0095
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
First and second semiconductor substrate samples formed with a first oxide layer with holes and a third semiconductor substrate sample formed with a second oxide layer having no hole are prepared. The first and the third samples are subject to the same contaminating process for contaminating the surface of the first oxide layer of the first sample and the surface within the hole, and the surface of the second oxide layer of the third sample. All of the first and second layers of the first to third samples are dissolved by the HF vapor. The dissolved solutions are collected and analyzed the amount of contaminating material contained in respective solutions. The contamination amount in the hole is derived from the first, second and third contamination amount from an equation: EQU contamination amount in the hole =first contamination amount-second contamination amount-(surface exposing ratio.times.third contamination amount) By this, in the process of fabrication of the semiconductor product, metal contaminant within the hole can be analyzed with high sensitivity, and can monitor washing effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.