Fabrication method of a vertical channel transistor
US5989961A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/87
Abstract
Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.