Semiconductor device having dual gate and method of formation
US5989962A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Sep 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The invention comprises a method of forming a semiconductor device is provided where a first gate insulator layer 26 is formed on an outer surface of semiconductor substrate 24. A mask body 28 is formed to cover portions of the insulator layer 26. The exposed portions of the layer 26 are subjected to a nitridation process to form a nitride layer 30. A second oxidation process forms a thick gate oxide layer 32. The nitride layer 30 inhibits the growth of oxide resulting in a single integrated device having gate insulator layers having two different thicknesses such that high voltage and low voltage transistors can be formed on the same integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.