Capacitor in a semiconductor configuration and process for its production

US5989972A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Dietrich Widmann · Unterhaching, DE
• Hanno Melzner · Sauerlach, DE
• Wolfgang Hoenlein · Unterhaching, DE

Key dates

• Filing date: Jul 24, 1996
• Grant date: Nov 23, 1999
• Expiry date: Jul 24, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/318

Abstract

A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping >10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.