Circuit structure which avoids latchup effect
US5990523A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.