Memory device with a cell array in triple well, and related manufacturing process

US5990526A · kind A · utility

Assignee

• STMicroelectronics SA

Inventors

• Roberto Bez · Milano, IT
• Alberto Modelli · Milano, IT

Key dates

• Filing date: Feb 20, 1998
• Grant date: Nov 23, 1999
• Expiry date: Feb 20, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over the second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over the second well in a second direction substantially orthogonal to the first direction and forming columns of memory cells, each strip of the second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over the second well in the second direction and intercalated to the strips of the second plurality, electrically co…