Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure
US5991521A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated-circuit design is provided which is represented by a hierarchial data structure. In accordance with the method and system of the present invention, an integrated-circuit design which includes at least one parent circuit represented by a set of parent circuit level data and at least one child circuit represented by a set of child circuit level data. For an open circuit connection within the child circuit, a determination is made as to whether or not the open circuit connection is permissible. In response to a determination that the open circuit connection is permissible, another determination is made as to whether or not the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit. In response to a determination that the number of I/O pins within the child circuit is greater than the number of open circuit connections within the child circuit, the set of child circuit level data is integrated into the set of parent circuit level data. Finally, a determination is made as to whether or not the open circuit connection is closed within the integrated set of parent circuit level data. An error message will b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.