Inventor · Austin, TX, US

Stephen T. Quay

36Patents

10h-index

32Co-inventors

75Inventor score

Filing activity: Mar 31, 1997 → Jun 5, 2019

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6117182A	Optimum buffer placement for noise avoidance	Physics	213	Expired
US6347393B1	Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation	Physics	212	Expired
US6401234B1	Method and system for re-routing interconnects within an integrated circuit design having blockages and bays	Physics	95	Expired
US7065730B2	Porosity aware buffered steiner tree construction	Physics	89	Expired
US6360350B1	Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms	Physics	26	Expired
US6044209A	Method and system for segmenting wires prior to buffer insertion	Physics	19	Expired
US7127696B2	Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management	Physics	17	Expired
US6591411B2	Apparatus and method for determining buffered steiner trees for complex circuits	Emerging Cross-Sectional Technologies	16	Expired
US7299442B2	Probabilistic congestion prediction with partial blockages	Physics	16	Expired
US6230302A	Method and system for performing timing analysis on an integrated circuit design	Physics	13	Expired
US7895557B2	Concurrent buffering and layer assignment in integrated circuit layout	Physics	10	Active
US6560752B1	Apparatus and method for buffer library selection for use in buffer insertion	Physics	9	Expired
US8365120B2	Resolving global coupling timing and slew violations for buffer-dominated designs	Physics	9	Active
US8881089B1	Physical synthesis optimization with fast metric check	Physics	8	Active
US7137081B2	Method and apparatus for performing density-biased buffer insertion in an integrated circuit design	Physics	8	Expired
US6898774B2	Buffer insertion with adaptive blockage avoidance	Physics	7	Expired
US7484199B2	Buffer insertion to reduce wirelength in VLSI circuits	Physics	6	Active
US7448007B2	Slew constrained minimum cost buffering	Physics	5	Active
US7676780B2	Techniques for super fast buffer insertion	Physics	5	Active
US9092591B2	Automatic generation of wire tag lists for a metal stack	Physics	5	Active
US8640075B2	Early design cycle optimzation	Physics	4	Active
US10831971B1	Net layer promotion with swap capability in electronic design	Physics	4	Active
US6915496B2	Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique	Physics	4	Expired
US8769468B1	Automatic generation of wire tag lists for a metal stack	Physics	4	Active
US5991521A	Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure	Physics	4	Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.