Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
US5991851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.