Enhanced Memory Systems, Inc.
19Patents
0Active
19Granted
29Portfolio score
Filing activity: Mar 14, 1996 → Jan 16, 2003
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5887272A | Enhanced DRAM with embedded registers | Emerging Cross-Sectional Technologies | 79 | Expired |
| US5875451A | Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM | Physics | 51 | Expired |
| US6330636A | Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank | Physics | 44 | Expired |
| US6151236A | Enhanced bus turnaround integrated circuit dynamic random access memory device | Physics | 35 | Expired |
| US5991851A | Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control | Physics | 32 | Expired |
| US6501698B1 | Structure and method for hiding DRAM cycle time behind a burst access | Physics | 15 | Expired |
| US6347357B1 | Enhanced DRAM with embedded registers | Emerging Cross-Sectional Technologies | 10 | Expired |
| US6064620A | Multi-array memory device, and associated method, having shared decoder circuitry | Physics | 9 | Expired |
| US6538928B1 | Method for reducing the width of a global data bus in a memory architecture | Physics | 9 | Expired |
| US6141281A | Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements | Physics | 8 | Expired |
| US6249840A | Multi-bank ESDRAM with cross-coupled SRAM cache registers | Physics | 6 | Expired |
| US6301183A | Enhanced bus turnaround integrated circuit dynamic random access memory device | Physics | 6 | Expired |
| US5963481A | Embedded enhanced DRAM, and associated method | Physics | 5 | Expired |
| US6055192A | Dynamic random access memory word line boost technique employing a boost-on-writes policy | Physics | 5 | Expired |
| US5835442A | EDRAM with integrated generation and control of write enable and column latch signals and method for making same | Physics | 3 | Expired |
| US6646928B2 | Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies | Physics | 3 | Expired |
| US6373751B1 | Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies | Physics | 2 | Expired |
| US6549472B2 | Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies | Physics | 1 | Expired |
| US6278646A | Multi-array memory device, and associated method, having shared decoder circuitry | Physics | 1 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.