Arithmetic built-in self test of multiple scan-based integrated circuits

US5991898A · kind A · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Janusz Rajski · West Linn, US
• Jerzy Tyszer · Poznań, PL

Key dates

• Filing date: Mar 10, 1997
• Grant date: Nov 23, 1999
• Expiry date: Mar 10, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318547
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.