Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure
US5994192A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a MOSFET device has been developed featuring a polycide gate structure, comprised of a metal silicide component, overlying a polysilicon component, and with the metal silicide shape intentionally fabricated to be narrower than the underlying polysilicon shape. This polycide configuration is obtained using an isotropic RIE procedure for the metal silicide shape, while using an anisotropic RIE procedure for the definition of the polysilicon shape. The undercut metal silicide shape can now accommodate a thermally grown oxide layer, thicker than the thermally grown oxide formed on the underlying, straight walled polysilicon shape, and thus allowing a lightly doped source and drain region, and the subsequent MOSFET channel length, to be defined by the thin oxide, on the sides of the straight walled polysilicon shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.