Add one process step to control the SI distribution of Alsicu to improved metal residue process window
US5994219A · kind A · utility
2Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jun 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of metal deposition with reduced metal residue after metal etching by cooling the wafer before metal deposition is described. A first patterned conducting layer is provided overlying a dielectric layer on the surface of a semiconductor substrate. The wafer is cooled to a temperature of less than about 20.degree. C. Thereafter, a metal layer is deposited overlying the first patterned conducting layer. The metal layer is etched away where it is not covered by a mask to complete formation of the metal line. Cooling of the wafer before metal deposition decreases the metal residue found after metal etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.