Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes
US5994228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Apr 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.