Memory cell configuration and method for its fabrication

US5994746A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Hans Reisinger · Grünwald, DE
• Reinhard Stengl · Stadtbergen, DE
• Franz Hofmann · Munich, DE
• Wolfgang Krautschneider · Ottobrunn, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Jan 15, 1999
• Grant date: Nov 30, 1999
• Expiry date: Jan 15, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.