MOSFETs with recessed self-aligned silicide gradual S/D junction
US5994747A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
Abstract
The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon oxynitride layer is formed on the side walls of the gate and refilled into the undercut portions to be used as a portion of the gate oxide. Side wall spacers are formed on the side walls of the gate. A polycide layer is formed at the top of the gate to reduce the electrical resistance. Source and drain regions are formed in the recessed portions of the substrate. Lightly doped drain (LDD) structures are formed in the substrate adjacent to the gate and under the gate oxide. Extended source and drain are formed between the source and drain and the LDD structure to suppress the short channel effect. Self-aligned silicide (SALICIDE) layers are formed at top of the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.