Semiconductor-on-insulator structure with reduced parasitic capacitance
US5994759A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.