Latch circuit and flip-flop circuit reduced in power consumption
US5994935A · kind A · utility
19Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.