CMOS twin-tub negative voltage switching architecture
US5994948A · kind A · utility
4Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Aug 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.