Synchronous memory test system
US5995424A · kind A · utility
120Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.