Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency
US5996064A · kind A · utility
25Cited by
6References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.