Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
US5996067A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Oct 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail <3:0> (218)) and a disabling pointer (head <3:0> (216))--and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating enable bits of one logic level from enable bits of an opposite logic level. The enable circuit includes several lookahead cells (702, 704, 706 and 708) arranged in an hierarchical array, each of the cells including bits that continue the hierarchical significance. Each cell receives an hierarchical portion of the enabling pointer 218 and the disabling pointer head <3:0> and a carry. From these pointers, the cell derives a generate, a propagate and the enable bits with a corresponding hierarchical significance. The propagates, generates and carries for all of the lookahead cells are interconnected using a circular propagate carry circuit (710) that provides for asserting a carry to a lookahead cell unless an intervening cell having a nonasserted propagate is interposed in the order of hier…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.