Process and structure for embedded DRAM

US5998251A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• H. J. Wu · Hsinchu, TW
• Shih-Wei Sun · Taipei, TW
• Jacob Chen · Hsinchu, TW
• Tri-Rung Yew · 東區, TW

Key dates

• Filing date: Nov 21, 1997
• Grant date: Dec 7, 1999
• Expiry date: Nov 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/31

Abstract

An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that …