Method of forming a semiconductor device having a stacked capacitor structure
US5998258A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
The present invention is a process for forming a lower capacitor electrode. Specifically, an oxygen tolerant bottom electrode layer (312) is formed over a conductive plug (216). A dielectric layer (420) is deposited and partially removed in order to form an inlaid bottom electrode structure. A capacitor dielectric (810) such as BST is formed over the lower electrode (310). The upper electrode (812) is formed over the capacitor dielectric (810) and the resulting stack is patterned in order to form a final capacitive device (916). In another embodiment of the present invention, a hardmask is formed over the bottom electrode (310) and removed prior to the capacitor dielectric (810) being formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.