Method of producing a read-only storage cell arrangement

US5998261A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Franz Hofmann · Munich, DE
• Wolfgang Rosner · Hersbruck, DE
• Wolfgang Krautschneider · Ottobrunn, DE
• Lothar Risch · Neubiberg, DE

Key dates

• Filing date: Dec 8, 1997
• Grant date: Dec 7, 1999
• Expiry date: Dec 8, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.