Method of forming high density flash memories with MIM structure
US5998264A · kind A · utility
Inventor
Key dates
| Filing date | Mar 11, 1999 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Mar 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain structure of the device is fabricated. Next, the side wall spacers is removed to expose a portion of the source and drain. Then, an undoped amorphous silicon layer is formed on the surface of the gate structure, the oxide layer and the exposed source and drain. A dry oxidation process is used to convert the amorphous silicon layer into textured tunnel oxide at the interface of the substrate and the oxide. A polysilicon layer is than formed, followed by chemical mechanical polishing the layer. A conductive layer is formed on the polysilicon layers. Subsequently, a silicon nitride layer deposited by jet vapor deposition (JVD) is formed on the conductive layer. A high k dielectric layer is next formed on the JVD nitride. A conductive layer to serve as control gate is subsequently formed on the high k dielectric layer. A patterning technique is used to pattern the layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.