Very dense chip package

US5998868A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• H. Bernhard Pogge · Hopewell Junction, US
• Bijan Davari · Mahopac, US
• Johann Greschner · Neckartenzlingen, DE
• Howard L. Kalter · Colchester, US

Key dates

• Filing date: Feb 4, 1998
• Grant date: Dec 7, 1999
• Expiry date: Feb 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit package or arrangement includes a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chips on the carrier. Top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The neighboring chips are separated by a gap G or spacing in a range of approximately 1 .mu.m<G.ltoreq.approximately 100 .mu.m. A metallic interconnect is disposed over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.