Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device
US5999198A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Sep 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.