Multilevel non-volatile memory devices
US5999445A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.