Byte-wide write scheme for a page flash device
US5999451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jul 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a floating gate memory that has a buffer that can be coupled to a set of floating gate memory cells in the memory, a method of writing to a selected portion of the set of floating gate cells. For example, a method of writing a byte to a floating gate memory where the memory uses a page buffer reads and writes to an entire row of cells at a time. Store contents of the set of floating gate cells into the buffer, store the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells, and store contents of the buffer into the set of floating gate cells. An improved floating gate memory is disclosed in which data may be loaded into a portion of the floating gate cells in a set of cells that may be coupled to a buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.