Circuit and method for internal refresh counter
US5999473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.