High speed memory self-timing circuitry and methods for implementing the same
US5999482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordline, and the model wordline is driven by a model wordline driver. The self-timing path also includes a model sense amplifier that is coupled to the model core cell through a pair of model bitlines. The model wordline and the pair of model bitlines are each coupled to a plurality of dummy core cells to approximate an RC delay of a worst case core cell of the array of core cells. Further, the model wordline is a folded wordline, such that the model wordline has a termination at a location that is proximate to the model wordline driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.