Caching in a multi-processor computer system
US6000007A · kind A · utility
66Cited by
17References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | May 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.