Apparatus for randomly sampling instructions in a processor pipeline
US6000044A · kind A · utility
115Cited by
17References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.