Daniel Leibholz
18Patents
9h-index
30Co-inventors
68Inventor score
Filing activity: Jun 29, 1990 → May 13, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6000044A | Apparatus for randomly sampling instructions in a processor pipeline | Physics | 115 | Expired |
| US6954846B2 | MICROPROCESSOR AND METHOD FOR GIVING EACH THREAD EXCLUSIVE ACCESS TO ONE REGISTER FILE IN A MULTI-THREADING MODE AND FOR GIVING AN ACTIVE THREAD ACCESS TO MULTIPLE REGISTER FILES IN A SINGLE THREAD MODE | Physics | 104 | Expired |
| US5103393A | Method of dynamically allocating processors in a massively parallel processing system | Physics | 80 | Expired |
| US6163840A | Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline | Physics | 65 | Expired |
| US7418582B1 | Versatile register file design for a multi-threaded processor utilizing different modes and register windows | Physics | 62 | Expired |
| US6195748A | Apparatus for sampling instruction execution information in a processor pipeline | Physics | 52 | Expired |
| US6098166A | Speculative issue of instructions under a load miss shadow | Physics | 52 | Expired |
| US6141734A | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | Physics | 39 | Expired |
| US6542987B1 | Method and circuits for early detection of a full queue | Physics | 17 | Expired |
| US7493615B2 | Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor | Physics | 9 | Expired |
| US6449713B1 | Implementation of a conditional move instruction in an out-of-order processor | Physics | 7 | Expired |
| US6675288B2 | Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | Physics | 6 | Expired |
| US6122728A | Technique for ordering internal processor register accesses | Physics | 6 | Expired |
| US6813702B1 | Methods and apparatus for generating effective test code for out of order super scalar microprocessors | Physics | 6 | Expired |
| US6704856B1 | Method for compacting an instruction queue | Physics | 6 | Expired |
| US6662293B1 | Instruction dependency scoreboard with a hierarchical structure | Physics | 5 | Expired |
| US6405304B1 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list | Physics | 5 | Expired |
| US8090930B2 | Method and circuits for early detection of a full queue | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.