Methods of forming integrated circuit capacitors using metal reflow techniques
US6001660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.