Hag-Ju Cho
25Patents
7h-index
32Co-inventors
69Inventor score
Filing activity: Nov 13, 1997 → Jul 8, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6509601B1 | Semiconductor memory device having capacitor protection layer and method for manufacturing the same | Electricity | 132 | Expired |
| US6821862B2 | METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES THAT INCLUDE A METAL OXIDE LAYER DISPOSED ON ANOTHER LAYER TO PROTECT THE OTHER LAYER FROM DIFFUSION OF IMPURITIES AND INTEGRATED CIRCUIT DEVICES MANUFACTURED USING SAME | Electricity | 75 | Expired |
| US6001660A | Methods of forming integrated circuit capacitors using metal reflow techniques | Electricity | 33 | Expired |
| US6096592A | Methods of forming integrated circuit capacitors having plasma treated regions therein | Electricity | 24 | Expired |
| US8293599B2 | Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials | Electricity | 10 | Active |
| US6740531B2 | Method of fabricating integrated circuit devices having dielectric regions protected with multi-layer insulation structures | Electricity | 8 | Expired |
| US7972950B2 | Method of fabricating semiconductor device having dual gate | Electricity | 7 | Active |
| US7390719B2 | Method of manufacturing a semiconductor device having a dual gate structure | Electricity | 6 | Active |
| US7507652B2 | Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure | Electricity | 5 | Active |
| US8313993B2 | Semiconductor device and method for fabricating the same | Electricity | 5 | Active |
| US11024631B2 | Integrated circuit device including field isolation layer and method of manufacturing the same | Electricity | 3 | Active |
| US7023037B2 | Integrated circuit devices having dielectric regions protected with multi-layer insulation structures | Electricity | 3 | Expired |
| US8557651B2 | Method of manufacturing a semiconductor device using an etchant | Electricity | 2 | Active |
| US8748239B2 | Method of fabricating a gate | Electricity | 2 | Active |
| US8524554B2 | Semiconductor device and method for fabricating the same | Electricity | 2 | Active |
| US7494859B2 | Semiconductor device having metal gate patterns and related method of manufacture | Electricity | 2 | Active |
| US9236313B2 | Method of fabricating semiconductor device having dual gate | Electricity | 1 | Active |
| US7531881B2 | Semiconductor devices having transistors with different gate structures and methods of fabricating the same | Electricity | 1 | Active |
| US8367502B2 | Method of manufacturing dual gate semiconductor device | Electricity | 1 | Active |
| US8119511B2 | Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same | Electricity | 0 | Active |
| US7892958B2 | Methods of fabricating semiconductor devices having transistors with different gate structures | Electricity | 0 | Active |
| US7399670B2 | Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed | Electricity | 0 | Active |
| US7727841B2 | Method of manufacturing semiconductor device with dual gates | Electricity | 0 | Active |
| US8501550B2 | Method of fabricating gate and method of manufacturing semiconductor device using the same | Electricity | 0 | Active |
| US8932922B2 | Method of fabricating semiconductor device having dual gate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.